1. Field of the Invention
The present invention relates to a semiconductor device and in particular, to a write control driver circuit for a high speed semiconductor device.
2. Background of the Related Art
FIG. 1 illustrates a related art write control driver circuit that includes a NAND-gate NAND11 for receiving a peri-top address transition detection signal ATDST and a peri-bottom address transition detection signal ATDSB, respectively. An inverter IN11 inverts an output signal from the NAND11 to output an address transition detection signal ATDS. A NAND-gate NAND12 receives a write enable signal WE and a chip selection signal CS. An inverter IN12 inverts an output signal from the NAND-gate NAND12 to output a write driver signal WD. A NAND-gate NAND13 receives a coding signal WEZ, the write driver signal WD and the combined address transition detection signal ATDS. An inverter IN13 inverts an output signal from the NAND-gate NAND13 to output a write control signal WC to a data transmission unit DT.
The peri-top address transition detection signal ATDST is a signal that is obtained by adding the address transition detection signals at the peri-top, and the peri-bottom address transition detection signal ATDSB is a signal that is obtained by adding the address transition detection signals at a peri-bottom. The write control signal WC is used to control the write operation where data from a data input buffer (not shown) is written onto a cell. In other words, the write control signal WC is a signal for enabling the data transmission unit DT.
The operation of the related art write control driver circuit will now be described. First, as shown in FIGS. 2D-2E, the peri-top address transition detection signal ATDST and the peri-bottom address transition detection signal ATDSB are generated by an address signal ADD, which is shown in FIG. 2A. The peri-top address transition detection signal ATDST and the peri-bottom address transition signal ATDSB are NANDed by the NAND-gate NAND11 and the result is inverted by the inverter IN11 to output the combined address transition detection signal ATDS. As shown in FIG. 2F, the pulse width of the combined address transition detection signal ATDS becomes wider than that of the individual peri-top address transition detection signal ATDST and the peri-bottom address transition detection signal ATDSB by a loading difference between the peri-top address transition detection signal ATDST and the peri-bottom address transition detection signal ATDSB.
In addition, the write enable signal WE and the chip selection signal CS are NANDed by the NAND-gate NAND12 and the result is inverted by the inverter IN12 to output the write driver signal WD. The write driver signal WD, the combined address transition detection signal ATDS, and the coding signal WEZ are NANDed by the NAND-gate NAND 13, and the result is inverted by the inverter IN13 to output the write control signal WC. The coding signal WBZ is preferably a signal output when the write enable signal WE and the signal from a Z-decoder (not shown) are combined by a NAND-gate (not shown).
When the write control signal WC is transited to a high level as shown in FIG. 2G, the data transmission unit DT is enabled and controlled by the write transmission transistor enable signal CWE. Accordingly, input data DATAIN from a data input buffer (not shown) is transmitted to and written into a cell as output data DATA and DATAB as shown in FIG. 2H. The write transmission transistor enable signal CWE is a signal for controlling a transmission transistor (not shown) of the data transmission unit DT.
Therefore, in the related art write control driver circuit, the write control signal WC is triggered when the combined address transition detection signal ATDS is transited to a high level. Since the pulse width of the combined address transition detection signal ATDS is wider than that of the two address transition detection signals ATDST and ATDSB, the write control signal WC is delayed by a predetermined time corresponding to the enabling time. For example, assume that the pulse width of the two address transition detection signals ATDST and ATDSB is 4 ns, and the peri-top address transition detection signal ATDST is delayed by 2 ns (rather than the peri-bottom address transition detection signal ATDSB) and then is loaded. In this case, the pulse width of the combined address transition detection signal ATDS is increased to 6 ns.
Therefore, in a high speed chip, it is becomes very difficult to accurately write the data onto the cells. For example, assume that a write AC parameter tAw is 12 ns in an operational requirements specification of a 1M SRAM. In the related art write control drive circuit, the signals are delayed by the combined address transition detection signal ATDS by 6 ns, a cell loading by 5 ns, and a write AC parameter margin tAs by 2 ns, respectively. Accordingly, the total delay time becomes 13 ns, which exceeds the write AC parameter tAw specification.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.